191 lines
6.4 KiB
C
191 lines
6.4 KiB
C
/*********************************************************************/
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/* Copyright 2009, 2010 The University of Texas at Austin. */
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/* All rights reserved. */
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/* */
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/* Redistribution and use in source and binary forms, with or */
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/* without modification, are permitted provided that the following */
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/* conditions are met: */
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/* */
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/* 1. Redistributions of source code must retain the above */
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/* copyright notice, this list of conditions and the following */
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/* disclaimer. */
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/* */
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/* 2. Redistributions in binary form must reproduce the above */
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/* copyright notice, this list of conditions and the following */
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/* disclaimer in the documentation and/or other materials */
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/* provided with the distribution. */
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/* */
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/* THIS SOFTWARE IS PROVIDED BY THE UNIVERSITY OF TEXAS AT */
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/* AUSTIN ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, */
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/* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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/* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */
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/* DISCLAIMED. IN NO EVENT SHALL THE UNIVERSITY OF TEXAS AT */
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/* AUSTIN OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, */
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/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */
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/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE */
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/* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR */
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/* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
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/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT */
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/* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE */
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/* POSSIBILITY OF SUCH DAMAGE. */
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/* */
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/* The views and conclusions contained in the software and */
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/* documentation are those of the authors and should not be */
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/* interpreted as representing official policies, either expressed */
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/* or implied, of The University of Texas at Austin. */
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/*********************************************************************/
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#ifndef CPUID_H
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#define CPUID_H
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#define VENDOR_INTEL 1
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#define VENDOR_UMC 2
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#define VENDOR_AMD 3
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#define VENDOR_CYRIX 4
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#define VENDOR_NEXGEN 5
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#define VENDOR_CENTAUR 6
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#define VENDOR_RISE 7
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#define VENDOR_SIS 8
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#define VENDOR_TRANSMETA 9
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#define VENDOR_NSC 10
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#define VENDOR_UNKNOWN 99
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#define BITMASK(a, b, c) ((((a) >> (b)) & (c)))
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#define FAMILY_80486 4
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#define FAMILY_P5 5
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#define FAMILY_P6 6
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#define FAMILY_PM 7
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#define FAMILY_IA64 8
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#if defined(__i386__) || defined(__x86_64__)
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#define GET_EXFAMILY 1
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#define GET_EXMODEL 2
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#define GET_TYPE 3
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#define GET_FAMILY 4
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#define GET_MODEL 5
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#define GET_APICID 6
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#define GET_LCOUNT 7
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#define GET_CHUNKS 8
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#define GET_STEPPING 9
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#define GET_BLANDID 10
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#define GET_FEATURE 11
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#define GET_NUMSHARE 12
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#define GET_NUMCORES 13
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#endif
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#ifdef __ia64__
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#define GET_ARCHREV 1
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#define GET_FAMILY 2
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#define GET_MODEL 3
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#define GET_REVISION 4
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#define GET_NUMBER 5
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#endif
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#define CORE_UNKNOWN 0
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#define CORE_80486 1
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#define CORE_P5 2
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#define CORE_P6 3
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#define CORE_KATMAI 4
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#define CORE_COPPERMINE 5
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#define CORE_NORTHWOOD 6
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#define CORE_PRESCOTT 7
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#define CORE_BANIAS 8
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#define CORE_ATHLON 9
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#define CORE_OPTERON 10
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#define CORE_BARCELONA 11
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#define CORE_VIAC3 12
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#define CORE_YONAH 13
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#define CORE_CORE2 14
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#define CORE_PENRYN 15
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#define CORE_DUNNINGTON 16
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#define CORE_NEHALEM 17
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#define CORE_ATOM 18
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#define CORE_NANO 19
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#define HAVE_SSE (1 << 0)
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#define HAVE_SSE2 (1 << 1)
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#define HAVE_SSE3 (1 << 2)
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#define HAVE_SSSE3 (1 << 3)
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#define HAVE_SSE4_1 (1 << 4)
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#define HAVE_SSE4_2 (1 << 5)
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#define HAVE_SSE4A (1 << 6)
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#define HAVE_SSE5 (1 << 7)
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#define HAVE_MMX (1 << 8)
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#define HAVE_3DNOW (1 << 9)
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#define HAVE_3DNOWEX (1 << 10)
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#define HAVE_CMOV (1 << 11)
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#define HAVE_PSE (1 << 12)
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#define HAVE_CFLUSH (1 << 13)
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#define HAVE_HIT (1 << 14)
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#define HAVE_MISALIGNSSE (1 << 15)
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#define HAVE_128BITFPU (1 << 16)
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#define HAVE_FASTMOVU (1 << 17)
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#define CACHE_INFO_L1_I 1
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#define CACHE_INFO_L1_D 2
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#define CACHE_INFO_L2 3
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#define CACHE_INFO_L3 4
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#define CACHE_INFO_L1_ITB 5
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#define CACHE_INFO_L1_DTB 6
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#define CACHE_INFO_L1_LITB 7
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#define CACHE_INFO_L1_LDTB 8
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#define CACHE_INFO_L2_ITB 9
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#define CACHE_INFO_L2_DTB 10
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#define CACHE_INFO_L2_LITB 11
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#define CACHE_INFO_L2_LDTB 12
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typedef struct {
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int size;
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int associative;
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int linesize;
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int shared;
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} cache_info_t;
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#define CPUTYPE_UNKNOWN 0
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#define CPUTYPE_INTEL_UNKNOWN 1
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#define CPUTYPE_UMC_UNKNOWN 2
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#define CPUTYPE_AMD_UNKNOWN 3
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#define CPUTYPE_CYRIX_UNKNOWN 4
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#define CPUTYPE_NEXGEN_UNKNOWN 5
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#define CPUTYPE_CENTAUR_UNKNOWN 6
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#define CPUTYPE_RISE_UNKNOWN 7
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#define CPUTYPE_SIS_UNKNOWN 8
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#define CPUTYPE_TRANSMETA_UNKNOWN 9
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#define CPUTYPE_NSC_UNKNOWN 10
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#define CPUTYPE_80386 11
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#define CPUTYPE_80486 12
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#define CPUTYPE_PENTIUM 13
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#define CPUTYPE_PENTIUM2 14
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#define CPUTYPE_PENTIUM3 15
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#define CPUTYPE_PENTIUMM 16
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#define CPUTYPE_PENTIUM4 17
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#define CPUTYPE_CORE2 18
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#define CPUTYPE_PENRYN 19
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#define CPUTYPE_DUNNINGTON 20
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#define CPUTYPE_NEHALEM 21
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#define CPUTYPE_ATOM 22
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#define CPUTYPE_ITANIUM 23
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#define CPUTYPE_ITANIUM2 24
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#define CPUTYPE_AMD5X86 25
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#define CPUTYPE_AMDK6 26
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#define CPUTYPE_ATHLON 27
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#define CPUTYPE_DURON 28
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#define CPUTYPE_OPTERON 29
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#define CPUTYPE_BARCELONA 30
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#define CPUTYPE_SHANGHAI 31
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#define CPUTYPE_ISTANBUL 32
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#define CPUTYPE_CYRIX5X86 33
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#define CPUTYPE_CYRIXM1 34
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#define CPUTYPE_CYRIXM2 35
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#define CPUTYPE_NEXGENNX586 36
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#define CPUTYPE_CENTAURC6 37
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#define CPUTYPE_RISEMP6 38
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#define CPUTYPE_SYS55X 39
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#define CPUTYPE_CRUSOETM3X 40
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#define CPUTYPE_NSGEODE 41
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#define CPUTYPE_VIAC3 42
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#define CPUTYPE_NANO 43
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#endif
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