mirror of
https://github.com/DualCoder/vgpu_unlock.git
synced 2024-05-08 06:12:57 +12:00
Add list of vGPUs and add PCI ID for Tesla T4.
This commit is contained in:
Jonathan Johansson
parent
6881c417ab
commit
cf01e2fbbd
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@ -36,7 +36,7 @@ Install the NVIDIA GRID vGPU driver, make sure to install it as a dkms module.
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./nvidia-installer
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```
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Modify the line begining with `ExecStart=` in `/lib/systemd/system/nvidia-vgpu.service`
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Modify the line begining with `ExecStart=` in `/lib/systemd/system/nvidia-vgpud.service`
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and `/lib/systemd/system/nvidia-vgpu-mgr.service` to use `vgpu_unlock` as
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executable and pass the original executable as the first argument. Ex:
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```
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20
vgpu_unlock
20
vgpu_unlock
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@ -112,10 +112,28 @@ script_source = r"""
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// TU102
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if(actual_devid == 0x1e02 || // TITAN RTX
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actual_devid == 0x1e04 || // RTX 2080 Ti
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actual_devid == 0x1e07) { // RTX 2080 Ti
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actual_devid == 0x1e07) { // RTX 2080 Ti Rev. A
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spoofed_devid = 0x1e30; // Quadro RTX 6000
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}
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// TU104
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if(actual_devid == 0x1e81 || // RTX 2080 Super
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actual_devid == 0x1e82 || // RTX 2080
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actual_devid == 0x1e84 || // RTX 2070 Super
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actual_devid == 0x1e87 || // RTX 2080 Rev. A
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actual_devid == 0x1e89 || // RTX 2060
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actual_devid == 0x1eb0 || // Quadro RTX 5000
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actual_devid == 0x1eb1) { // Quadro RTX 4000
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spoofed_devid = 0x1eb8; // Tesla T4
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}
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// GA102
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if(actual_devid == 0x2204 || // RTX 3090
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actual_devid == 0x2205 || // RTX 3080 Ti
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actual_devid == 0x2206) { // RTX 3080
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spoofed_devid = 0x2235; // RTX A40
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}
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devid_ptr.writeU16(spoofed_devid);
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}
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@ -561,7 +561,7 @@ static void vgpu_unlock_hmac_sha256(void* dst,
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*/
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/* Debug logs can be enabled here. */
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#if 0
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#if 1
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#define LOG(...) printk(__VA_ARGS__)
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#else
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#define LOG(...)
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@ -572,6 +572,87 @@ static void vgpu_unlock_hmac_sha256(void* dst,
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#define VGPU_UNLOCK_KEY_PHYS_BEG (0xf0029634)
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#define VGPU_UNLOCK_KEY_PHYS_END (VGPU_UNLOCK_KEY_PHYS_BEG + 0x10)
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typedef struct {
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uint8_t num_blocks; /* Number of 16 byte blocks up to 'sign'. */
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uint16_t unk0;
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uint16_t dev_id;
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uint16_t vend_id; /* Check skipped if zero. */
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uint16_t subsys_id;
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uint16_t subsys_vend_id; /* Check skipped if zero. */
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uint8_t unk1[7];
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char name[15];
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uint8_t sign[0x20];
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}
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__attribute__((packed))
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vgpu_unlock_vgpu_t;
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static vgpu_unlock_vgpu_t vgpu_unlock_vgpu[] =
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{
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/* Tesla P40 */
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{ 2, 0x1007, 0x1b38, 0, 0x11e7, 0, { 0 }, { "GRID P40-1B" } },
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{ 2, 0x1007, 0x1b38, 0, 0x11e8, 0, { 0 }, { "GRID P40-1Q" } },
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{ 2, 0x1007, 0x1b38, 0, 0x11e9, 0, { 0 }, { "GRID P40-2Q" } },
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{ 2, 0x1007, 0x1b38, 0, 0x11ea, 0, { 0 }, { "GRID P40-3Q" } },
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{ 2, 0x1007, 0x1b38, 0, 0x11eb, 0, { 0 }, { "GRID P40-4Q" } },
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{ 2, 0x1007, 0x1b38, 0, 0x11ec, 0, { 0 }, { "GRID P40-6Q" } },
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{ 2, 0x1007, 0x1b38, 0, 0x11ed, 0, { 0 }, { "GRID P40-8Q" } },
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{ 2, 0x1007, 0x1b38, 0, 0x11ee, 0, { 0 }, { "GRID P40-12Q" } },
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{ 2, 0x1007, 0x1b38, 0, 0x11ef, 0, { 0 }, { "GRID P40-24Q" } },
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{ 2, 0x1007, 0x1b38, 0, 0x11f0, 0, { 0 }, { "GRID P40-1A" } },
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{ 2, 0x1007, 0x1b38, 0, 0x11f1, 0, { 0 }, { "GRID P40-2A" } },
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{ 2, 0x1007, 0x1b38, 0, 0x11f2, 0, { 0 }, { "GRID P40-3A" } },
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{ 2, 0x1007, 0x1b38, 0, 0x11f3, 0, { 0 }, { "GRID P40-4A" } },
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{ 2, 0x1007, 0x1b38, 0, 0x11f4, 0, { 0 }, { "GRID P40-6A" } },
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{ 2, 0x1007, 0x1b38, 0, 0x11f5, 0, { 0 }, { "GRID P40-8A" } },
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{ 2, 0x1007, 0x1b38, 0, 0x11f6, 0, { 0 }, { "GRID P40-12A" } },
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{ 2, 0x1007, 0x1b38, 0, 0x11f7, 0, { 0 }, { "GRID P40-24A" } },
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{ 2, 0x1007, 0x1b38, 0, 0x1287, 0, { 0 }, { "GRID P40-2B" } },
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{ 2, 0x1007, 0x1b38, 0, 0x12ef, 0, { 0 }, { "GRID P40-2B4" } },
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{ 2, 0x1007, 0x1b38, 0, 0x133a, 0, { 0 }, { "GRID P40-1B4" } },
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{ 2, 0x1007, 0x1b38, 0, 0x137e, 0, { 0 }, { "GRID P40-24C" } },
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{ 2, 0x1007, 0x1b38, 0, 0x1381, 0, { 0 }, { "GRID P40-4C" } },
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{ 2, 0x1007, 0x1b38, 0, 0x1382, 0, { 0 }, { "GRID P40-6C" } },
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{ 2, 0x1007, 0x1b38, 0, 0x1383, 0, { 0 }, { "GRID P40-8C" } },
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{ 2, 0x1007, 0x1b38, 0, 0x1384, 0, { 0 }, { "GRID P40-12C" } },
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/* Tesla P4 */
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{ 2, 0x1007, 0x1bb3, 0, 0x1203, 0, { 0 }, { "GRID P4-1B" } },
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{ 2, 0x1007, 0x1bb3, 0, 0x1204, 0, { 0 }, { "GRID P4-1Q" } },
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{ 2, 0x1007, 0x1bb3, 0, 0x1205, 0, { 0 }, { "GRID P4-2Q" } },
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{ 2, 0x1007, 0x1bb3, 0, 0x1206, 0, { 0 }, { "GRID P4-4Q" } },
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{ 2, 0x1007, 0x1bb3, 0, 0x1207, 0, { 0 }, { "GRID P4-8Q" } },
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{ 2, 0x1007, 0x1bb3, 0, 0x1208, 0, { 0 }, { "GRID P4-1A" } },
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{ 2, 0x1007, 0x1bb3, 0, 0x1209, 0, { 0 }, { "GRID P4-2A" } },
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{ 2, 0x1007, 0x1bb3, 0, 0x120a, 0, { 0 }, { "GRID P4-4A" } },
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{ 2, 0x1007, 0x1bb3, 0, 0x120b, 0, { 0 }, { "GRID P4-8A" } },
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{ 2, 0x1007, 0x1bb3, 0, 0x1288, 0, { 0 }, { "GRID P4-2B" } },
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{ 2, 0x1007, 0x1bb3, 0, 0x12f1, 0, { 0 }, { "GRID P4-2B4" } },
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{ 2, 0x1007, 0x1bb3, 0, 0x133c, 0, { 0 }, { "GRID P4-1B4" } },
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{ 2, 0x1007, 0x1bb3, 0, 0x1380, 0, { 0 }, { "GRID P4-8C" } },
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{ 2, 0x1007, 0x1bb3, 0, 0x1385, 0, { 0 }, { "GRID P4-4C" } },
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/* Tesla T4 */
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{ 2, 0x1007, 0x1e30, 0, 0x1309, 0, { 0 }, { "GRID T4-1B" } },
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{ 2, 0x1007, 0x1e30, 0, 0x130a, 0, { 0 }, { "GRID T4-2B" } },
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{ 2, 0x1007, 0x1e30, 0, 0x130b, 0, { 0 }, { "GRID T4-2B4" } },
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{ 2, 0x1007, 0x1e30, 0, 0x130c, 0, { 0 }, { "GRID T4-1Q" } },
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{ 2, 0x1007, 0x1e30, 0, 0x130d, 0, { 0 }, { "GRID T4-2Q" } },
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{ 2, 0x1007, 0x1e30, 0, 0x130e, 0, { 0 }, { "GRID T4-4Q" } },
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{ 2, 0x1007, 0x1e30, 0, 0x130f, 0, { 0 }, { "GRID T4-8Q" } },
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{ 2, 0x1007, 0x1e30, 0, 0x1310, 0, { 0 }, { "GRID T4-16Q" } },
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{ 2, 0x1007, 0x1e30, 0, 0x1311, 0, { 0 }, { "GRID T4-1A" } },
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{ 2, 0x1007, 0x1e30, 0, 0x1312, 0, { 0 }, { "GRID T4-2A" } },
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{ 2, 0x1007, 0x1e30, 0, 0x1313, 0, { 0 }, { "GRID T4-4A" } },
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{ 2, 0x1007, 0x1e30, 0, 0x1314, 0, { 0 }, { "GRID T4-8A" } },
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{ 2, 0x1007, 0x1e30, 0, 0x1315, 0, { 0 }, { "GRID T4-16A" } },
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{ 2, 0x1007, 0x1e30, 0, 0x1345, 0, { 0 }, { "GRID T4-1B4" } },
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{ 2, 0x1007, 0x1e30, 0, 0x1375, 0, { 0 }, { "GRID T4-16C" } },
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{ 2, 0x1007, 0x1e30, 0, 0x139a, 0, { 0 }, { "GRID T4-4C" } },
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{ 2, 0x1007, 0x1e30, 0, 0x139b, 0, { 0 }, { "GRID T4-8C" } },
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{ 0 } /* Sentinel */
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};
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static const uint8_t vgpu_unlock_magic_sacrifice[0x10] = {
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0x46, 0x4f, 0x39, 0x49, 0x74, 0x91, 0xd7, 0x0f,
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0xbc, 0x65, 0xc2, 0x70, 0xdd, 0xdd, 0x11, 0x54
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@ -618,8 +699,24 @@ static uint16_t vgpu_unlock_pci_devid_to_vgpu_capable(uint16_t pci_devid)
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/* TU102 */
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case 0x1e02: /* TITAN RTX */
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case 0x1e04: /* RTX 2080 Ti */
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case 0x1e07: /* RTX 2080 Ti */
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case 0x1e07: /* RTX 2080 Ti Rev. A*/
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return 0x1e30; /* Quadro RTX 6000 */
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/* TU104 */
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case 0x1e81: /* RTX 2080 Super */
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case 0x1e82: /* RTX 2080 */
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case 0x1e84: /* RTX 2070 Super */
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case 0x1e87: /* RTX 2080 Rev. A */
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case 0x1e89: /* RTX 2060 */
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case 0x1eb0: /* Quadro RTX 5000 */
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case 0x1eb1: /* Quadro RTX 4000 */
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return 0x1eb8; /* Tesla P4 */
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/* GA102 */
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case 0x2204: /* RTX 3090 */
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case 0x2205: /* RTX 3080 Ti */
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case 0x2206: /* RTX 3080 */
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return 0x2235; /* RTX A40 */
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}
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return pci_devid;
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@ -650,8 +747,8 @@ static void *vgpu_unlock_find_in_rodata(const void *val, size_t size)
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{
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uint8_t *i;
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for (i = (uint8_t*)&vgpu_unlock_nv_kern_rodata_beg;
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i < (uint8_t*)&vgpu_unlock_nv_kern_rodata_end - size;
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for (i = &vgpu_unlock_nv_kern_rodata_beg;
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i < &vgpu_unlock_nv_kern_rodata_end - size;
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i++)
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{
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if (vgpu_unlock_memcmp(val, i, size) == 0)
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@ -694,6 +791,10 @@ static void vgpu_unlock_apply_patch(void)
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void **sac_sign_ptr;
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vgpu_unlock_aes128_ctx aes_ctx;
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uint16_t *pci_info;
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vgpu_unlock_vgpu_t* vgpu;
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uint8_t first_block[0x10];
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uint16_t device_id;
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char* name;
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magic = vgpu_unlock_find_in_rodata(vgpu_unlock_magic,
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sizeof(vgpu_unlock_magic));
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@ -784,40 +885,53 @@ static void vgpu_unlock_apply_patch(void)
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goto failed;
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}
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memcpy(sac_magic, vgpu_unlock_magic, sizeof(vgpu_unlock_magic));
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memcpy(*sac_blocks_ptr, *blocks_ptr, num_blocks * 0x10 + 1);
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/* Decrypt the first block so we can access the PCI device ID. */
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memcpy(first_block, (uint8_t*)*blocks_ptr + 1, sizeof(first_block));
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vgpu_unlock_aes128_init(&aes_ctx, vgpu_unlock_key);
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for (i = 0; i < num_blocks; i++)
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vgpu_unlock_aes128_decrypt(&aes_ctx, first_block);
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LOG(KERN_WARNING "Decrypted first block is: %16ph.\n",
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first_block);
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device_id = *((uint16_t*)first_block + 1);
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device_id = vgpu_unlock_pci_devid_to_vgpu_capable(device_id);
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/* Loop over all vGPUs and add the ones that match our device ID. */
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vgpu = vgpu_unlock_vgpu;
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while (vgpu->num_blocks != 0)
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{
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vgpu_unlock_aes128_decrypt(&aes_ctx,
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(uint8_t*)*sac_blocks_ptr + 1 + i * 0x10);
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LOG(KERN_WARNING "Decrypted block is: %16ph.\n",
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(uint8_t*)*sac_blocks_ptr + 1 + i * 0x10);
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if (vgpu->dev_id != device_id)
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{
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vgpu++;
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continue;
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}
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num_blocks = vgpu->num_blocks;
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*sac_magic_ptr = vgpu_unlock_magic;
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*sac_blocks_ptr = vgpu;
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*sac_sign_ptr = &vgpu->sign;
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vgpu_unlock_aes128_init(&aes_ctx, vgpu_unlock_key);
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for (i = 0; i < num_blocks; i++)
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{
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vgpu_unlock_aes128_encrypt(&aes_ctx,
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(uint8_t*)vgpu + 1 + i * 0x10);
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}
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vgpu_unlock_hmac_sha256(&vgpu->sign,
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vgpu,
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1 + num_blocks * 0x10,
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vgpu_unlock_key,
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sizeof(vgpu_unlock_key));
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sac_magic_ptr += 3;
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sac_blocks_ptr = sac_magic_ptr + 1;
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sac_sign_ptr = sac_magic_ptr + 2;
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vgpu++;
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}
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pci_info = (uint16_t*)((uint8_t*)*sac_blocks_ptr + 1);
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pci_info[1] = vgpu_unlock_pci_devid_to_vgpu_capable(pci_info[1]);
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pci_info[2] = 0;
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pci_info[3] = 0x11ec;
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pci_info[4] = 0;
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vgpu_unlock_aes128_init(&aes_ctx, vgpu_unlock_key);
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for (i = 0; i < num_blocks; i++)
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{
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vgpu_unlock_aes128_encrypt(&aes_ctx,
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(uint8_t*)*sac_blocks_ptr + 1 + i * 0x10);
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}
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vgpu_unlock_hmac_sha256(*sac_sign_ptr,
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*sac_blocks_ptr,
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1 + num_blocks * 0x10,
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vgpu_unlock_key,
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sizeof(vgpu_unlock_key));
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vgpu_unlock_patch_applied = TRUE;
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LOG(KERN_WARNING "vGPU unlock patch applied.\n");
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